1. Field of the Invention
The invention relates to the design and testing of integrated circuits. More specifically, the invention relates to a method and an apparatus performing timing analysis of integrated circuits.
2. Related Art
As the complexity, density, and operating frequencies of integrated circuits has increased, signal timing and signal integrity within integrated circuits have become more difficult to maintain. Thus, signal timing analysis should be performed during the design stage of an integrated circuit to increase the likelihood of an acceptable performance of a manufactured integrated circuit. In general EDA (electronic design automation) tool manufacturers use timing libraries for standard cells used in the design of integrated circuits. These timing libraries include timing arc based models for various predefined input signals (waveforms) and various output load capacitance values. While the timing arc based models provide accurate timing for the isolated logic cells, they have difficulties with logic cells embedded within integrated circuit because the shapes of the input signals do not exactly match the waveform shape used during timing model characterization and the load circuit on output of the logic cell is often not a lumped capacitor used during timing characterization but a “coupled networks”, i.e. networks of signal nets subject to cross talk and noise from nearby signal nets.
For example, as illustrated in FIG. 1(a), a logic cell 110, which receives an original input signal O_IN_S, provides a final output signal F_OUT_S on a signal net 121, which runs through coupled network 120. Coupled network 120 also includes signal nets 123 and 125. While signal nets 121, 123, and 125 are not physically connected through conducting paths, parasitic capacitances cause a capacitive coupling between signal nets 123 and 121 as represented by parasitic capacitor 124 (note parasitic capacitors are drawn using dashed lines rather than solid lines and have grey background shading). Similarly, signal nets 125 and 121 have parasitic coupling represented by parasitic capacitor 126. In FIG. 1(a), multiple parasitic capacitances are illustrated using a single lumped capacitor. However, in actual coupled networks, the parasitic capacitances are distributed and behave as multiple distributed capacitors. The parasitic coupling of the signal nets in coupled network 120 may cause cross talk and other noise issues for final output signal F_OUT_S of logic cell 110.
Because each chip design results in different forms of coupled networks for each logic cell (e.g. logic cell 110), the timing arc based models can not adequately cover the use of logic cells in coupled networks. Accordingly, the use of timing arc based models is generally limited for uncoupled timing analysis and for very simplified timing analysis using lumped effective capacitance or other approximation for the coupled networks. For example, FIG. 1(b) illustrates a typical circuit that is suited for timing arc based models. Specifically, a logic cell 140, which receives original input signal O_IN_S, drives a final output signal F_OUT_S on signal net 151 in simplified network 150. Original input signal O_IN_S must match a predefined input signal provided with the timing arc based model of logic cell 140. Simplified network 150 may approximate parasitic capacitance using simple lumped effective capacitance or other approximations for parasitic capacitances from other signal nets on signal net 151. In this situation the timing arc based model provides an accurate characterization of final output signal F_OUT_S. However, the timing arc based models do not provide accurate results in a coupled network.
In addition to difficulties with coupled networks, timing arc based models are difficult to use with input signals having “distorted waveforms”, i.e. signals that are not very similar to one of the predefined input signals used during timing model characterization. For example, in an integrated circuit, the output signal of a first logic cell is often fed to the input signal of a second logic cell. Even if the effects of coupled networks are not present, the output signal of the first logic cell is unlikely to exactly match one of the predefined input signals for the timing arc based models.
FIG. 1(c) illustrates another method for timing analysis. However the method illustrated in FIG. 1(c) is only suited for small logic circuits for the reasons described below. Specifically, a small logic cell 160, which receives an original input signal O_IN_S, provides a final output signal F_OUT_S on a signal net 171, which runs through coupled network 170. Coupled network 170 also includes signal nets 173 and 175. While signal nets 171, 173, and 175 are not physically connected through conducting paths, parasitic capacitances cause a capacitive coupling between signal nets 173 and 171 as represented by parasitic capacitor 174. Similarly, signal nets 175 and 171 have parasitic coupling represented by parasitic capacitor 176. Small logic cell 160 is divided into one or more channel connected blocks which are illustrated using channel connected blocks (CCB) 161 through 169. As used herein, the term channel connected block (which is well known in the art) refers to a group of transistors whose channels are connected with each other. Channel connected blocks could also have parasitic elements such as capacitors and resistors along with the afore-mentioned transistors. Due to space constraints additional channel connected blocks that may exist between CCB 161 and 169 are not shown. Channel connected block (CCB) based current models are used for each channel connected block of small logic cell 160. Channel connected block (CCB) based current models can be used for coupled network timing analysis. CCB based current models are often based on a dc current table where CCB current is a function of input and output voltage values of that CCB. In addition, CCB based current models can often be used in a time stepper to interact with an arbitrary input waveform shape and an arbitrary RLC coupled load network to produce a piecewise linear output waveform. However, due to the complexity of the CCB-based current models, in practice only very simple circuits (i.e. consisting of only a few CCBs) like inverters, buffers, NAND gates, NOR gates, and certain AOI and OAI gates, etc. can be fully modeled using CCB based current models. Channel connected block based current models are described in U.S. Patent Application 20070010981, entitled “Modeling Circuit Cells for Waveform Propagation” by Ding et al.
For more complex logic cells, often only the boundary layers of transistor level logics are modeled using CCB based current models using techniques such as the one, described in “TBNM—Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks” by Jindrich Zejda and Li Ding Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED '06) 2006.
Due to the lack of pre-characterized information on the internal transistor level structure of the complex logic cells, existing CCB based timing analysis method does not apply to complex logic cells. Hence there is a need for a method and apparatus for timing analysis on complex circuits in coupled networks.